1. Technical Field
The present invention relates generally to the field of semiconductor manufacturing and, more specifically, to a method for forming double gated field effect transistors.
2. Background Art
The need to remain cost and performance competitive in the production of semiconductor devices has caused continually increasing device density in integrated circuits. To facilitate the increase in device density, new technologies are constantly needed to allow the feature size of these semiconductor devices to be reduced.
The push for ever increasing device densities is particularly strong in CMOS technologies, such as the in the design and fabrication of field effect transistors (FETs). FETs are used in almost all types of integrated circuit design (i.e., microprocessors, memory, etc.) Unfortunately, increased device density in CMOS FET can result in degradation of performance and/or reliability.
One type of FET that is used in many different applications is a dual gate FET. A dual gate FET has two separate gates in series that are used to control the operation of the FET. For example, in a dual gate NFET, both gates must be high for the transistor to be on. If either gate is low, the transistor does not turn on. Likewise, in a dual gate PFET, both gates must be low for the transistor to be on. If either gate is high, the transistor will not turn on.
Dual gate FETs have many different uses today. Dual gate FETs are used in logic operations, effectively providing a logical NAND operation with one device. Dual gate FETs are also commonly used in radio frequency application where the dual gate structure can be used to provide additional isolation between the drain and the gate. This reduces the possibility of capacitive feedback from the drain back to the gate, and thus improves operation of the device.
Unfortunately, several difficulties arise in the design and fabrication of dual gate transistors. For example, it has been difficult to design dual gate transistors with sufficient device density and current control ability when compared to single gate transistors. This has limited their application to low performance applications.
Thus, there is a need for improved device structures and methods of fabrications of dual gate devices that provide improved device performance and device density.